1. Field of the Invention
The present invention generally relates to high power communication systems. More specially, the present invention relates to high efficiency high power amplifiers for such systems.
2. The Prior Art
In modern digital wireless communication systems, such as IS-95, PCS, WCDMA, OFDM and so on, the power amplifiers have advanced towards having a wide bandwidth and large number of carriers. Recently, orthogonal frequency division multiplexing (OFDM) modulation is an attractive technique for transmitting information efficiently within a limited bandwidth like WiBRO and WiMAX. However, since the OFDM signal consists of a number of independently modulated sub-carriers, it produces a higher peak-to-average power ratio (PAR) signal. A typical PAR for a 64-subcarrier OFDM signal is around 8-13 dB. When the number of sub-carriers is increased to 2048, the PAR also increases, typically from 11 to 16 dB. The power amplifiers designed to operate with these high PARs typically have significantly deteriorated efficiency.
The Doherty amplifier is known as a technique for improving the efficiency at high output back-off power. Its primary advantage is the ease of configuration when applied to high power amplifiers, unlike other efficiency enhancement amplifiers or techniques such as switching mode amplifiers, EER, LINC and so on. Recent results have been reported on its use as: a symmetric Doherty structure, an asymmetric Doherty structure with uneven power transistors, and a N-way Doherty structure using multi-paralleled transistors. In the case of the symmetric Doherty amplifier, the maximum efficiency point is obtained at 6 dB back-off power.
The asymmetric Doherty amplifier can obtain a high efficiency at various back-off powers using a combination of different power device sizes for the main and peaking amplifiers. Unfortunately, it is difficult to optimize the gain and output power of the asymmetric Doherty amplifier because of the different device matching circuits and the delay mismatch between the main amplifier and the peaking amplifier.
The conventional N-way Doherty amplifier has an efficiency enhancement over a conventional 2-way Doherty structure by using multiple parallel transistors of identical devices. Its one drawback is that the total gain will be reduced due to the loss of the N-way input power splitter. Under low gain situations this will increase the power dissipation of the driving amplifier.
Further, while the conventional N-way Doherty amplifier can offer improved efficiency at high output back-off power, the performance of conventional N-way Doherty amplifiers deteriorates as to both gain and efficiency for higher peak-to-average power ratio (PAPR) signals.
Hence, a need remains in the arts for a method of applying both circuit-level and system-level techniques simultaneously for improving the gain and efficiency performance of N-way Doherty amplifier at high output back-off power in the high power communication systems.